AI chip
Rival AMD has announced plans to invest more than $10 billion across Taiwan’s semiconductor ecosystem, striking partnerships with ASE, SPIL and Powertech Technology. Today’s GPUs and CPUs frequently combine anywhere from 10 to 20 distinct chips into a single package. Because training and running large models requires immense amounts of data to move between compute dies and memory banks without delay, aI chips rely heavily on this integration.
“Packaging was always that thing that you just didn’t worry about,” former Intel CEO Pat Gelsinger, now a partner at Playground Global, said recently in Taipei. Notably, Nvidia is not alone in funding external capacity. For decades, packaging was an afterthought aimed at encasing chips in plastic or ceramic to protect them and connect them to circuit boards. That dynamic has flipped as shrinking transistors onto single silicon slabs becomes increasingly difficult and expensive. Gelsinger estimates advanced packaging could eventually account for as much as half of a chip’s total value.
Nvidia is reportedly pouring billions of dollars into expanding advanced chip-packaging capacity at a Taiwanese supplier as severe manufacturing bottlenecks threaten to slow the delivery of high-performance artificial intelligence (AI) processors. The move comes as the global race to build AI infrastructure has unleashed unprecedented capital into advanced packaging – a stage of semiconductor manufacturing once viewed as routine, but now standing as the primary choke point in producing next-generation hardware. Taiwan Semiconductor Manufacturing Company (TSMC) currently dominates the market for the most sophisticated packaging technologies, primarily Chip-on-Wafer-on-Substrate (CoWoS). This method mounts individual silicon dies, such as processors and high-bandwidth memory, onto a shared base so they can transfer data at high speeds. CoWoS is essential for processors designed by Nvidia, AMD and Broadcom, as well as custom silicon created by major cloud providers. However, TSMC’s limited packaging capacity has left chip designers scrambling to find alternatives.