The latest launch follows the April debut of the TPU 8t and TPU 8i at Google Cloud Next, which offered up to 2.7 times better training performance and 80% better inference price performance, respectively, compared to the previous generation. The announcement marks the first time the company has introduced four different TPU systems in a single year.
Combined with recent PyTorch integrations, Google says the new SoCs are part of a broader push to pair modular hardware with an open software stack, making TPUs as easy to use as general-purpose hardware for everyday developers. Google is expanding its eighth-generation Tensor Processing Unit (TPU) lineup with two new specialised chips: the TPU 8tx and the TPU 8i Max.
In its announcement, Google drew a clear line between designing a new chip and building a new system. Creating a brand-new chip is laying out billions of microscopic transistors on silicon, and it is a multi-year process bound by physics and complex manufacturing timelines. A system, by contrast, focuses on how compute, networking, storage and packaging are arranged around existing silicon.
Because it packs twice as much silicon into an existing rack footprint, data centers get significantly higher compute density per square foot and per watt. Anticipating that AI software would evolve faster than chip manufacturing, Google designed its TPUs as modular building blocks within its AI Hypercomputer architecture. By adjusting packaging, high-speed memory, optical networking and security around the core chips, Google can deliver specialised supercomputers in months rather than years. The TPU 8tx is the third system in the eighth-generation family, built specifically for regulated enterprises and governments running proprietary models or autonomous agents alongside sensitive data. Normally, data is encrypted while stored or traveling over a network, but must be unlocked in memory while a computer actively processes it. Built on the same silicon as the training-focused TPU 8t and paired with 5th Generation AMD EPYC CPU hosts, the TPU 8tx embeds security directly into the hardware layer. This keeps sensitive data and model weights isolated and protected even while in active use. The fourth system, TPU 8i Max, targets a different bottleneck: the “memory wall. When dozens of AI agents work simultaneously across an entire software codebase or hours of video, memory bandwidth quickly runs out. To solve this, Google combined two low-latency TPU 8i chips onto a single package. This dual-chip setup scales compute and memory together, delivering double the compute, double the SRAM, and double the HBM bandwidth of a standard TPU 8i. TPU 8i: Low-latency, real-time reasoning that cuts inter-chip communication delays by up to half.